The present disclosure relates generally to superscalar computing, and more particularly to methods, systems and computer program products for identifying and tracking frequently accessed registers in a superscalar processor.
Modern central processing units (CPU) have a superscalar out-of-order architecture. A superscalar CPU implements a form of instruction-level parallelism within a single processor. It allows faster CPU throughput and executes more instructions in a unit of time. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different—execution units on the processor such as an arithmetic logic unit, a shifter, or a multiplier. The superscalar aspect brings the benefit of ‘workload optimization’ (e.g. a single instruction multiple data streams (SIMD) engine optimizes vector processing). Out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. A processor executes instructions in an order governed by the availability of input data, not necessarily in their original order in a program. In doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and to retrieve data for the next instruction in a program, processing instead the next instructions which are able to run immediately and independently.
For a superscalar processor, large multi-ported registers are implemented to support multiple instructions being executed at the same time. The architected registers are allocated by a compiler or an application binary interface (ABI) definitions depending on the workload, some registers are used more than others. Register area can be reduced drastically if the number of register port is reduced for registers that are not accessed frequently. Only the frequently accessed registers are fully ported.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.